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| WED2DL32512V 512Kx32 Synchronous Pipeline Burst SRAM FEATURES s Fast clock speed: 200, 166, 150 & 133MHz s Fast access times: 2.5ns, 3.5ns, 3.8ns & 4.0ns s Fast OE access times: 2.5ns, 3.5ns, 3.8ns 4.0ns s Single +3.3V power supply (VDD) s Separate +3.3V or +2.5V isolated output buffer supply (VDDQ) s Snooze Mode for reduced-power standby s Single-cycle deselect s Common data inputs and data outputs s Individual Byte Write control and Global Write s Clock-controlled and registered addresses, data I/Os and control signals s Burst control (interleaved or linear burst) s Packaging: * 119-bump BGA package s Low capacitive bus loading PRELIMINARY* DESCRIPTION The WEDC SyncBurst - SRAM family employs high-speed, lowpower CMOS designs that are fabricated using an advanced CMOS process. WEDC's 16Mb SyncBurst SRAMs integrate two 512K x 16 SRAMs into a single BGA package to provide 512K x 32 configuration. All synchronous inputs pass through registers controlled by a positive-edge-triggered single-clock input (CLK). The synchronous inputs include all addresses, all data inputs, active LOW chip enable (CE), burst control input (ADSC) and byte write enables (BW0-3). Asynchronous inputs include the output enable (OE), clock (CLK) and snooze enable (ZZ). There is also a burst mode input (MODE) that selects between interleaved and linear burst modes. Write cycles can be from one to four bytes wide, as controlled by the write control inputs. Burst operation can be initiated with the address status controller (ADSC) input. * This data sheet describes a product under development, not fully characterized, and is subject to change without notice. FIG. 1 1 A B C D E F G H J K L M N P R T U VDDQ NC NC DQc DQc VDDQ DQc DQc VDDQ DQd DQd VDDQ DQd DQd NC NC VDDQ PIN CONFIGURATION (TOP VIEW) 2 SA SA SA NC DQc DQc DQc DQc VDD DQd DQd DQd DQd NC SA NC DC 3 SA SA SA VSS VSS VSS BWc VSS NC VSS BWd VSS VSS VSS MODE SA DC 4 NC ADSC VDD NC CE OE NC NC VDD CLK NC BWE SA1 SA0 VDD SA DC 5 SA SA SA VSS VSS VSS BWb VSS NC VSS BWa VSS VSS VSS NC SA DC 6 SA SA SA NC DQb DQb DQb DQb VDD DQa DQa DQa DQa NC SA NC NC 7 VDDQ NC NC DQb DQb VDDQ DQb DQb VDDQ DQa DQa VDDQ DQa DQa NC ZZ VDDQ BWc BWd SA CLK ADSC OE BWE CE MODE ZZ BWa BWb BLOCK DIAGRAM 512K x 16 SSRAM DQa DQb 512K x 16 SSRAM DQc DQd NOTE: DC = Do Not Connect January 2000 Rev. 0 1 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com WED2DL32512V PIN DESCRIPTION x36 CLK 4P 4N 2A, 2C, 2R, 2B 3A, 3B, 3C, 3T 4T, 5A, 5B, 5C, 5T, 6A, 6B, 6C, 6R 5L 5G 3G 3L 4M 4K 4E 7T 4F 4B Symbol Input SA0 SA1 SA Type Pulse Input Description The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock. Synchronous Address Inputs: These inputs are registered and must meet the setup and hold times around the rising edge of CLK. BWa BWb BWc BWd BWE CLK CE ZZ OE ADSC Input Synchronous Byte Write Enables: These active LOW inputs allow individual bytes to be written and must meet the setup and hold times around the rising edge of CLK. A byte write enable is LOW for a WRITE cycle and HIGH for a READ cycle. BWa controls DQa's and DQPa; BWb controls DQb's and DQPb; BWc controls DQc's and DQPc; BWd controls DQd's and DQPd. Byte Write Enable: This active LOW input permits BYTE WRITE operations and must meet the setup and hold times around the rising edge of CLK. Clock: This signal registers the address, data, chip enable, byte write enables and burst control inputs on its rising edge. All synchronous inputs must meet setup and hold times around the clock's rising edge. Synchronous Chip Enable: This active LOW input is used to enable the device and conditions the internal use of ADSP. CE is sampled only when a new external address is loaded. Snooze Enable: This active HIGH, asynchronous input causes the device to enter a low-power standby mode in which all data in the memory array is retained. When active, all other inputs are ignored. Output Enable: This active LOW, asynchronous input enables the data I/O output drivers. Synchronous Address Status Controller: This active LOW input interrupts any ongoing burst, causing a new external address to be registered. A READ or WRITE is performed using the new address if CE is LOW. ADSC is also used to place the chip into power-down state when CE is HIGH. Mode: This input selects the burst sequence. A LOW on MODE selects "linear burst." NC or HIGH on this input selects "interleaved burst." Do not alter input state while device is operating. SRAM Data I/Os: Byte "a" is DQa's; Byte "b" is DQb's; Byte "c" is DQc's; Byte "d" is DQd's. Input data must meet setup and hold times around rising edge of CLK. Input Input Input Input Input Input 3R (a) 6K, 6L, 6M, 6N, 7K, 7L, 7N, 7P (b) 6E, 6F, 6G, 6H, 7D, 7E, 7G, 7H (c) 1D, 1E, 1G, 1H 2E, 2F, 2G, 2H (d) 1K, 1L, 1N, 1P, 2K, 2L, 2M, 2N 2J, 4C, 4J, 4R, 5R, 6J 1A, 1F, 1J, 1M 1U 7A, 7F, 7J, 7M, 7U 3D, 3E, 3F, 3H, 3K, 3M, 3N, 3P, 5D, 5E, 5F, 5H, 5K, 5M, 5N, 5P 2U 3U 4U 5U MODE DQa DQb DQc DQd VDD VDDQ VSS Input Input/ Output Supply Supply Supply Power Supply: See DC Electrical Characteristics and Operating Conditions for range. Isolated Output Buffer Supply: See DC Electrical Characteristics and Operating Conditions for range. Ground: GND. TMS TDI TDO TCK Input Input Output Input Scan Test Mode Select Scan Test Data In Scan Test Data Out Scan Test Clock White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com 2 WED2DL32512V INTERLEAVED BURST TABLE First Address External X...X00 X...X01 X...X10 X...X11 Second Address Internal X...X01 X....X00 X...X11 X...X10 (MODE = NC OR HIGH) Fourth Address Internal X...X11 X...X10 X...X01 X...X00 INTERLEAVED BURST TABLE First Address External X...X00 X...X01 X...X10 X...X11 Second Address Internal X...X01 X....X10 X...X11 X...X00 (MODE = LOW) Fourth Address Internal X...X11 X...X00 X...X01 X...X10 Third Address Internal X...X10 X...X11 X...X00 X...X01 Third Address Internal X...X10 X...X11 X...X00 X...X01 TRUTH TABLE Function Deselected Cycle, Power-Down Deselected Cycle, Power-Down SNOOZE MODE, Power-Down WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Begin Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst READ Cycle, Suspend Burst WRITE Cycle, Suspend Burst WRITE Cycle, Suspend Burst Address Used None None None External External External Current Current Current Current Current Current CE H L X L L L X X H H X H ZZ L L H L L L L L L L L L ADSC L L X L L L H H H H H H WRITE X X X L H H H H H H L L OE X X X X L H L H L H X X CLK L-H L-H X L-H L-H L-H L-H L-H L-H L-H L-H L-H DQ High-Z High-Z High-Z D Q High-Z Q High-Z Q High-Z D D NOTES: 1. X means "Don't Care." ---- means active LOW. H means logic HIGH. L means logic LOW. 2. For WRITE, L means any one or more byte write enable signals (BWa, BWb, BWc or BWd) and BWE are LOW. 3. BWa enables WRITEs to DQa's and DQPa. BWb enables WRITEs to DQb's. BWc enables WRITEs to DQc's. BWd enables WRITEs to DQd's. 4. All inputs except OE and ZZ must meet setup and hold times around the rising edge (LOW to HIGH) of CLK. 5. Wait states are inserted by suspending burst. 6. For a WRITE operation following a READ operation, OE must be HIGH before the input data setup time and held HIGH throughout the input data hold time. 7. This device contains circuitry that will ensure the outputs will be in High-Z during power-up. 3 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com WED2DL32512V PARTIAL TRUTH TABLE - WRITE COMMANDS Function BWE BWa BWb BWc BWd Read H X X X X Read L H H H H Write Byte "a" L L H H H Write All Bytes L L L L L NOTE: Using BWE and BWa through BWd, any one or more bytes may be written. ABSOLUTE MAXIMUM RATINGS* Voltage on VDD Supply relative to VSS Voltage on VDDQ Supply relative to VSS VIN (DQx) VIN (Inputs) Storage Temperature (BGA) Short Circuit Output Current -0.5V to +4.6V -0.5V to +4.6V -0.5V to VDDQ +0.5V -0.5V to VDD +0.5V -55C to +125C 100 mA *Stress greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. ELECTRICAL CHARACTERISTICS Description Input High (Logic 1)Voltage Input Low (Logic 0) Voltage Input Leakage Current Ouptut Leakage Current Output High Voltage Output Low Voltage Supply Voltage Symbol VIH VIL ILI ILO VOH VOL VDD Conditions Min 2.0 -0.3 Max VDD +0.3 0.8 1.0 1.0 -- 0.4 3.6 V Units V V mA mA V V V Notes 1 1 2 1 1 1 0V VIN VDD Output(s) disabled, 0V VIN VDD IOH = -4.0mA IOL = 8.0mA 3.134 -1.0 -1.0 2.4 -- 3.135 3.6 Isolated Output Buffer SupplyVDDQ NOTES: 1. All voltages referenced to Vss (GND). 2. MODE has an internal pull-up, and input leakage = 10A. DC CHARACTERISTICS Description Power Supply Current: Operating CMOS Standby TTL Standby Clock Running Symbol IDD ISB2 ISB3 ISB4 Conditions Device selected; All inputs VIL or 3 VIH; Cycle time 3 tKC MIN; VDD = MAX; Outputs open Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD - 0.2; All inputs static; CLK frequency = 0 Device deselected; VDD = MAX; All inputs VIL or VIH; All inputs static; CLD frequency = 0 Device deselected; VDD = MAX; All inputs VSS + 0.2 or VDD -0.2; Cycle time 3 tKC MIN Typ 200* MHz 950 10 20 80 20 40 220 166 MHz 800 20 40 180 150 MHz 740 20 40 160 133 MHz 600 20 40 140 Units mA mA mA mA Notes 1,2,3 2,3 2,3 2,3 * Advanced Information NOTES: 1. IDD is specified with no output current and increases with faster cycle times. IDD increases with faster cycle times and greater output loading. 2. "Device deselected" means device is in power-down mode as defined in the truth table. "Device selected" means device is active (not in power-down mode). 3. Typical values are measured at 3.3V, 25C and 133MHz. BGA CAPACITANCE Description Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance NOTES: 1. This parameter is sampled. Conditions TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz TA = 25C; f = 1MHz Symbol CI CO CA CCK Typ 3 4 3 2.5 Max 6 5 5 4 Units pF pF pF pF Notes 1 1 1 1 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com 4 WED2DL32512V AC CHARACTERISTICS Symbol Parameter Clock Clock Cycle Time Clock Frequency Clock HIGH Time Clock LOW Time Output Times Clock to output valid Clock to output invalid (2) Clock to output on Low-Z (2,3,4) Clock to output in High-Z (2,3,4) OE to output valid (5) OE to output in Low-Z (2,3,4) OE to output in High Z (2,3,4) Setup Times Address (6,7) Address status (ADSC) (6,7) Write signals (BWa-BWd, BWE) (6,7) Data-in (6,7) Chip enables (CE) (6,7) Hold Times Address (6,7) Address status (ADSC) (6,7) Write Signals (BWa-BWd, BWE) (6,7) Data-in (6,7) Chip Enables (CE) (6,7) tAH tADSH tWH tDH tCEH 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 0.5 ns ns ns ns ns tKQ tKQX tKQLZ tKQHZ tOEQ tOELZ tOEHZ tAS tADSS tWS tDS tCES 1.5 1.5 1.5 1.5 1.5 0 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0 3.0 2.5 0 3.5 1.5 1.5 1.5 1.5 1.5 2.5 1.25 0 3.5 3.5 0 3.8 1.5 1.5 1.5 1.5 1.5 3.5 1.25 0 3.8 3.8 0 4.0 3.8 1.5 0 4.0 4.0 4.0 ns ns ns ns ns ns ns ns ns ns ns ns tKC tKF tKH tKL Min 5.0 200 2.0 2.0 2.4 2.4 200MHz Max 166MHz Min Max 6.0 166 2.6 2.6 150MHz Min 6.6 150 2.6 2.6 Max Min 7.5 133 133MHz Max Units ns MHz ns ns NOTES: 1. Test conditions as specified with the output loading as shown in Figure 1 for 3.3V 1/0 and Figure 3 for 2.5V 1/0 unless otherwise noted. 2. This parameter is measured with output load as shown in Figure 2 for 3.3V 1/0 and Figure 4 for 2.5V 1/0. 3. This parameter is sampled. 4. Transition is measured 500mV from steady state voltage. 5. OE is a "Don't Care" when a byte write enable is sampled LOW. 6. A WRITE cycle is defined by at least one byte write enable LOW for the required setup and hold times. A READ cycle is defined by all byte write enables HIGH and ADSC LOW for the required setup and hold times. 7. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK when ADSC is LOW and chip enabled. All other synchronous inputs must meet the setup and hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at each rising edge of CLK when ADSC is LOW to remain enabled. OUTPUT LOADS Output Z0 == 50 Z0 50 Parameter Input Pulse Levels AC TEST CONDITIONS 3.3V I/O VSS to 3.0 1 1.5 1.5 2.5V I/O VSS to 2.5 1 1.25 1.25 Unit V ns V V 50 Input Rise and Fall Times Input Timing Reference Levels Output Timing Reference Levels Output Load Vt Vt 1.5V for 3.3V I/O = = 1.5V Vt = 1.25V for 2.5V I/O AC Output Load Equivalent See figure, at left 5 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com WED2DL32512V SNOOZE MODE SNOOZE MODE is a low-current, "power-down" mode In which the device is deselected and current is reduced to ISB2Z. The duration of SNOOZE MODE is dictated by the length of time ZZ is in a HIGH state. After the device enters SNOOZE MODE, all inputs except ZZ become gated inputs and are ignored. ZZ is an asynchronous, active HIGH input that causes the device to enter SNOOZE MODE. When ZZ becomes a logic HIGH, ISB2Z is guaranteed after the setup time tZZ is met. Any READ or WRITE operation pending when the device enters SNOOZE MODE is not guaranteed to complete successfully. Therefore, SNOOZE MODE must not be initiated until valid pending operations are completed. SNOOZE MODE Description Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to snooze current ZZ inactive to exit snooze current Conditions ZZ VIH Symbol ISB2Z tZZ tRZZ tZZI tRZZI Min Max 10 2(tKC) 2(tKC) Units mA ns ns ns ns Notes 1 1 1 1 2(tKC) FIG. 2 SNOOZE MODE TIMING DIAGRAM CLOCK tZZ ZZ tRZZ tZZI ISUPPLY tRZZI IISB2Z ALL INPUTS (except ZZ) DESELECT or READ Only Output (Q) HIGH-Z DON'T CARE White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com 6 WED2DL32512V FIG. 3 READ TIMING DIAGRAM tKHKH tKHKL tKLKH CLK tSCVKH tKHSC X ADSC tEVKH CE tKHEX tAVKH ADDR A1 tKHAX A2 A3 A4 A5 OE tOELQ X tOELQ V tOEHQZ WRITE tKHQ Z tKHQX tKHQ V DQ Q(A1) Q(A2) Q(A2+1) Q(A2+2) Q(A2+3) DON'T CARE UNDEFINED NOTES: 1. Q (A2) refers to output from address A2. Q (A2+1) refers to output from the next internal burst address following A2. 7 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com WED2DL32512V FIG. 4 WRITE TIMING DIAGRAM tKHK H tKHKL tKLKH CLK t SC VKH tKHSCX ADSC t EVKH CE t KHEX t AVKH ADDR A1 t KHAX A2 A3 A4 A5 OE t WVKH KHG WX t KHWX WRITE t DVK H t KHDX DQ D(A1) D(A2) D(A3) D (A4) D(A5) DON'T CARE UNDEFINED NOTES: 1. D (A2) refers to output from address A2. D (A2+1) refers to output from the next internal burst address following A2. 2. OE must be HIGH before the input data setup and held HIGH throughout the data hold time. This prevents input/output data content in for the time period prior to the byte write enable inputs being sampled. 3. Full-width WRITE can be initiated by BWE, BWa, - BWd LOW. Timing is shown assuming that the device was not enabled before entering into its sequence. OE does not cause Q to be driven until after the following clock rising edge. White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com 8 WED2DL32512V PACKAGE DIMENSION: 7.62 (0.300) TYP 119 BUMP PBGA 2.79 (0.110) MAX R 1.52 (0.060) MAX (4x) A B C D E F G A1 CORNER 14.00 (0.551) TYP 1.27 (0.050) TYP 22.00 (0.866) TYP 20.32 (0.800) TYP H J K L M N P R T U 1.27 (0.050) TYP 0.711 (0.028) MAX ALL LINEAR DIMENSIONS ARE MILLIMETERS AND PARENTHETICALLY IN INCHES ORDERING INFORMATION 512Kx32 Part Number Config. tKQ (ns) 2.5 3.5 3.8 4.0 3.8 4.0 Clock (MHz) 200 166 150 133 150 133 Package No. 435 435 435 435 435 435 Commercial Temp Range (0C to 70C) WED2DL32512V25BC WED2DL32512V35BC WED2DL32512V38BC WED2DL32512V40BC 512Kx32 512Kx32 512Kx32 512Kx32 Industrial Temp Range (-40C to +85C)* WED2DL32512V38BI 512Kx32 WED2DL32512V40BI 512Kx32 * Advanced Information 9 White Electronic Designs Corporation * (508) 366-5151 * www.whiteedc.com |
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